When stacking a plurality of semiconductor chips in one package for miniaturization and/or high functionality of a resulting semiconductor device, such as a NAND type electrically erasable programmable read-only memory (EEPROM), a through silicon via (TSV) may be used to transmit and receive an electrical signal at a high speed between the plurality of semiconductor chips. The TSV electrically connects electrodes, which are provided on a front surface and a rear surface of each of the semiconductor chips, through a conductive via that passes through the substrate of the semiconductor chip.
When stacking the semiconductor chips and interconnecting electrodes between the semiconductor chips, the semiconductor chips are also bonded together with an adhesive. However, the semiconductor chips are thinned for reducing the thickness of the resulting semiconductor device, and thus, warping of the individual semiconductor chips may occur. The warping of the semiconductor chips widens a gap between the adjacent semiconductor chips in the stack of semiconductor chips, for example, at corners of adjacent semiconductor chips in the stack. If the semiconductor chips are flattened during assembly into the stacked device, where the stress in any of the semiconductor chips is greater than an adhesive strength of the adhesive holding adjacent semiconductor chips together, the semiconductor chip may peel away from the adhesive at the corner of the semiconductor chip.